1. Field of the Invention
This invention relates to a semiconductor memory with well structure, and more particularly to a dynamic random access memory (DRAM) with CMOS structure.
2. Description of the Related Art
In the conventional DRAM, CMOS structure has not been employed to constitute the peripheral circuit of the memory cell array. Recently, however, use of DRAMs with CMOS structure is growing.
FIG. 1 shows an example of the cross section of a one-transistor/one-capacitor type DRAM with CMOS structure. In FIG. 1, 1 denotes a P-type Si body; 2 and 2*, P-wells formed in the same manufacturing step; 3, an N-well; 4, an insulation film for a capacitor; 5, a capacitor electrode; 6, the gate insulation film of a transistor; 7, the gate electrode of a transistor; 8 and 8*, N.sup.+ -type diffusion layers (source, drain); 9, P.sup.+ -type diffusion layers (source, drain); 10, an insulation film; 11, an Al wiring layer; A, a memory cell section; and B, the peripheral circuit thereof. P-well layer 2 is formed to have an impurity concentration higher than that of P-type substrate 1.
Recently, it was found preferable to form a memory cell in a high impurity concentration well in order to prevent a soft error.
In a conventional memory device, the impurity concentration of P-well 2*, in which the memory cell is formed, is the same as that of P-well 2, in which the peripheral circuit is formed. Therefore, it becomes necessary to further increase the impurity concentration of the well for the memory cell in order to suppress the soft error. From the circuit characteristic point of view, it is not desirable to excessively increase the impurity concentration of the well because it will increase the diffusion capacitance between N.sup.+ -type layer 8* and P-well 2* and lower the Junction breakdown voltage. If the miniaturization technique of the IC internal structure is further advanced, it becomes necessary to operate the internal circuit on a voltage of 2 to 4V, despite the fact that the input/output circuit section of the IC is operated on a voltage of 5V. Thus, it becomes necessary to adequately change the impurity concentration of the well, such as P-wells 2 and 2*, according to the difference in the power source voltages. However, no practical technology has developed to meet the requirement.